This invention relates to a semiconductor device and more particularly to a semiconductor device in which conductive layers constituting two different elements spatially overlap each other as in an MOS dynamic random access memory, and a method of manufacturing the same.
In recent years, the integrated circuit technique has achieved a remarkable progress. In particular, the process of effecting high integration, that is, the extreme miniaturization of IC elements has advanced at a surprisingly high speed. Above all, a double-layer polysilicon structure of a semiconductor device has made a prominent contribution to the high integration and extreme miniaturization of IC elements. This double-layer polysilicon technique is characterized by causing part of the polysilicon conductive layer of one of two different adjacent MOS field effect elements formed on the same substrate to be superposed on the polysilicon conductive layer of the other MOS field effect element with an insulation layer interposed therebetween, and the degree of integration is advanced by reducing a space defined between two different elements as much as possible.
The double-layer polysilicon structure has another advantage that a contact between a second polysilicon layer and an overlying aluminum wire is effected at a point above the region of a first polysilicon layer, thereby prominently progressing the degree of integration. Where, however, a pattern is chosen to have as fine a width as 3 to 4 microns in order to prominently elevate the degree of integration, then an inter-layer insulation film has to be formed by wet oxidation, giving rise to a number of problems. Description is now given of the difficulties accompanying the abovementioned double-layer structure process, with reference to the MOS dynamic random access memory (referred to as MOS dynamic RAM) to which said double-layer structure is particularly applied.
With the MOS dynamic RAM of the present day, a plurality of memory cells, in each of which one transistor 1 and one capacitor 2 shown in FIG. 1 jointly constitute one bit are arranged, as shown in FIG. 2, in the directions of the row and column on a semiconductor chip 5, thereby providing memory arrays 6. Those portions of the chip which cause external data to be written in the memory cell, and conversely cause data to be read out of the memory cell and generate memory cell-actuating signals are collectively referred to as a "peripheral circuit 7". The transistor 3 of FIG. 1 is included in the peripheral circuit 7. The gate electrode of the transistor 1 and the electrode of the capacitor 2 both included in each of the abovementioned memory cells 6 are fabricated with the overlapping double-layer polysilicon structure. The gate electrode of the peripheral circuit 7 is formed when the first or second polysilicon layer is produced, thus constituting the ordinary single layer polysilicon structure. Referring to FIG. 1, line W is a word line, and line B is a bit line.
FIG. 3 is a sectional view of a semiconductor device constituted by an IC version of the circuit of FIG. 1. The transistor 3 of FIG. 1 comprises a source region 11, drain region 12, gate oxide film 13 and gate electrode 14 all formed in or on a semiconductor substrate 10. The capacitor 2 of FIG. 1 is formed of an insulation layer 15 and electrode 16. The transistor 1 of FIG. 1 is constituted by a gate oxide film 17, gate electrode 18, etc. As seen from FIG. 3, the electrode 16 of the capacitor 2 and part of the gate electrode 18 of the transistor 1 spatially overlap each other with an insulation layer 19 interposed therebetween. FIG. 4 is an enlarged view of the section IV of FIG. 3, and FIG. 5 is also an enlarged view of the section V of FIG. 3.
With the above-mentioned conventional semiconductor device-manufacturing method, insulation layers 19, 19' are provided by wet oxidizing first polysilicon conductive layers 14, 16 after said conductive layers have been patterned in order to ensure insulation between first polysilicon conductive layer 16 and a second polysilicon conductive layer 18. However, the conventional wet oxidation process has the drawbacks that while an insulation layer is grown by the oxidation of the substrate 10 and the first polysilicon conductive layers 14, 16, the edges of said conductive layers 14, 16 often tend to be turned up. On the other hand, the impurities used for the formation of the regions 11, 12 of the transistor 3 are likely to be diffused by self alignment technics into the substrate by using the first polysilicon conductive layers 14, 16 as diffusion mask. Since the edges of the first polysilicon conductive layers 14, 16 are turned up, the above-mentioned impurities are ready to spread through the substrate more in the horizontal direction thereof, thereby prominently shortening the effective channel length of the transistor 3. FIG. 6A and FIG. 6B illustrate the defect of the conventional wet oxidation process used in producing a semiconductor device in comparison with the ordinary dry oxidation process applied in manufacturing an insulation gate type semiconductor device. FIG. 6A is a sectional view of an MOS transistor included in the peripheral circuit of a double-layer polysilicon structure type semiconductor device and fabricated by the aforesaid prior art wet oxidation process. FIG. 6B is a sectional view of an MOS transistor produced by the ordinary chemical vapor deposition and dry oxidation process. With the widths L.sub.1, L.sub.2 of the polysilicon electrodes of FIGS. 6A and 6B taken to be 4 microns and the diffusion depth Xj of FIGS. 6A and 6B assumed to be 0.4 micron, then a difference between the effective channel length l.sub.2 of the MOS transistor of FIG. 6B and the effective channel length l.sub.1 of the MOS transistor of FIG. 6A is as large as 0.7 micron.
The effective channel length of an MOS transistor set in a large scale integration (LSI) circuit has to be defined with great care in consideration of, for example, an undesirable short channel effect and punch-through withstand voltage. The width of a polysilicon electrode is generally determined by adding the extent to which an impurity is diffused in a substrate in the horizontal direction thereof to the predetermined channel length of the MOS transistor. This means that in the case of the semiconductor device having the double-layer polysilicon structure as shown in FIG. 6A, the width of a polysilicon electrode has to be extended by 0.7 micron as a result of the afore-mentioned turned up condition of the edges of the first polysilicon conductive layer. The extension of the width of a polysilicon electrode leads to an enlarged area of a chip. Further, the enlarged width of a polysilicon electrode results in a corresponding rise in the gate capacity, undesirably retarding the operation of a semiconductor device and increasing its power consumption.
A more important problem is that prominent variations occur in the threshold voltage of the MOS transistor. As previously described, the turned up condition of the edges of the polysilicon electrode causes an impurity to be more noticeably diffused in the horizontal direction of a substrate, allowing variations to take place more readily in the threshold voltage of the MOS transistor due to the objectionable short channel effect. Consequently where, for example, an MOS dynamic RAM is applied, then the sensitivity of a sensing circuit falls under the above-mentioned condition.
Further with the prior art semiconductor device-manufacturing method, a memory cell region in which the first polysilicon conductive layer 16 and second polysilicon conductive layer 18 overlap each other has a greater height than the peripheral circuit region by the thickness of said second polysilicon conductive layer 18. The presence of such stepped portion reduces the precision with which a pattern is resolved through an IC mask, prominently obstructing the fine communication of IC elements.